hv758 features hvcmos technology for high performance high density integration ultrasound transmitter 0 to 90v output voltage 2.2a source and sink current in pw mode 580ma source and sink current in cw mode up to 20mhz operating frequency matched delay times 1.2v to 5.0v cmos logic interface built-in output drain bleed resistors application medical ultrasound imaging piezoelectric transducer drivers ndt ultrasound transmission pulse waveform generator ? ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex hv758 is a four-channel, monolithic high voltage, high-speed pulse generator. it is designed for medical ultrasound applications. this high voltage and high-speed integrated circuit can also be used for other piezoelectric, capacitive or mems transducers in ultrasonic nondestructive detection and sonar ranger applications. the hv758 comprises a controller logic interface circuit, level translators, mosfet gate drives and high current power p- channel and n-channel mosfets as the output stage for each channel. the output current limit can be set to one of four levels by using two mode control inputs. the output stages of each channel are designed to provide peak output currents over 2.5a when in mode 4, with up to 180v swings. when in mode 1, the output stages reduce the peak current to 580ma for cw mode operation, which reduces the power dissipation of the ic. the power mosfet gate drivers are supplied by two ? oating 10vdc power supplies referenced to v pp and v nn . this direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the pcb layout easier. typical application circuit quad high speed 90v 2.2a ultrasound pulser nin1 sub v pp -10v v pf v dd +10v g ref v pp 0 to +90v en mc1 c1 v nn 0 to -90v txn1 v nn +10v 1 of 4 channels c2 c3 c5 c4 txp1 hv out 1 x1 d1 d2 v nf v sub v ll +1.8 to 3.3v +90v c6 c7 en_pwr mc0 otp v ss pin1 r p1 r n1 rgnd +1.8 to 3.3v logic hv758 rgnd p-driver n-driver level translator level translator
2 hv758 ordering information device package options 64-ball fcbga 8x8mm body, 2.45mm height (max), 0.8mm pitch hv758 hv758fb HV758FB-G absolute maximum ratings parameter value v ss , power supply reference 0v v ll , positive logic supply -0.5v to +7.0v v dd , positive logic and level translator supply -0.5v to +14v (v pp - v pf ) positive ? oating gate drive supply -0.5v to +14v (v nf - v nn ) negative gate ? oating drive supply -0.5v to +14v (v pp - v nn ) differential high voltage supply +190v v pp , high voltage positive supply -0.5v to +95v v nn , high voltage negative supply +0.5v to -95v otp, over temperature protection output -0.5v to +7.0v all logic input pin x , nin x and en voltages -0.5v to +7.0v (v sub - v pp ) substrate to v pp voltage difference +190v (v pp - txp x ) v pp to txp x voltage difference +190v (v sub - txp x ) substrate to txp x voltage difference +190v (txn x - v nn ) txn x to v nn voltage difference +190v operating temperature -40c to +125c storage temperature -65c to +150c thermal resistance, ja , (4 layer, 1oz., 4x3, 36-via pcb) 12.8c/w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. power-up sequence 1v sub 2v ll with logic signal low 3v dd 4(v pp - v pf ) and (v nf - v nn ) 5v pp and v nn 6 logic control signals power-down sequence 1 all logic signals go to low 2v pp and v nn 3(v pp - v pf ) and (v nf - v nn ) 4v dd 5v ll 6v sub pin con? guration package marking a b c d e f g h 1 2 3 4 5 6 7 8 64-ball fcbga (top view) yy = year sealed ww = week sealed l = lot number = green packaging yyww hv758fb lllllllll 64-ball fcbga -g indicates package is rohs compliant (green)
3 hv758 operating supply voltages and current (4 channel active) (operating conditions, unless otherwise speci? ed, v ss = 0v, v ll = +3.3v, v dd = +10v, v pp -v pf = +10v, v nn -v nf = -10v, v pp =+90v, v nn = -90v, t a = 25c) symbol parameter min typ max units conditions v ll logic voltage reference 1.2 2.5 5.0 v --- v dd internal voltage supply 7.5 12 12.6 v --- v pf positive gate driver supply (v pp -12.6) (v pp -12) (v pp -7.5) v floating driver voltage supplies equals v dd . v nf negative gate drive supply (v nn +7.5) (v nn +12) (v nn +12.6) v v sub ic substrate voltage v dd v pp +90 v must be the most positive potential of the ic. v pp positive hv supply 0 - +90 v --- v nn negative hv supply -90 - 0 v --- sr max allowable slew rate on v pp, v nn - - 25 v/s --- i ll v ll current en = low - 125 250 a --- i ddq v dd current en = low - 100 - a --- i dden v dd current en = high - 1.1 2.0 ma f = 0mhz i dden v dd current mode = 4 - 3.2 - ma f = 5.0mhz, continuous, no loads i ddencw v dd current mode = 1 - 3.1 - ma i ppq v pp current en = low - 74 90 a f = 0mhz i ppen v pp current mode = 4 - 258 - ma f = 5.0mhz, continuous, no loads i ppencw v pp current mode = 1 - 215 - ma i nnq v nn current en = low - 78 90 a f = 0mhz i nnen v nn current mode = 4 - 258 - ma f = 5.0mhz, continuous, no loads i nnencw v nn current mode = 1 - 215 - ma i pfq v pf current en = low - 37 70 a f = 0mhz i pfen v pf current mode = 4 - 70 - ma f = 5.0mhz, continuous, no loads i pfencw v pf current mode = 1 - 9.0 - ma i nfq v nf current en = low - 35 70 a f = 0mhz i nfen v nf current mode = 4 - 42 - ma f = 5.0mhz, continuous, no loads i nfencw v nf current mode = 1 - 6.0 - ma note: all supply current values are for reference only. under voltage and over temperature protection symbol parameter min typ max units conditions v pull_up open drain pull-up voltage - - 5.0 v --- v uvdd v dd threshold 3.5 5.7 7.0 v --- v uvll v ll threshold 0.8 0.9 1.0 v --- v uvvf v pf , v nf threshold 2.7 4.0 5.4 v --- v ol_otp otp ? ag output low voltage - - 1.0 v v ll = 2.5v, otp = active, i pull_up = 1.0ma. i otp max. open drain output current - 1.0 - ma --- t otp over-temperature threshold 95 110 125 c if over-temperature occurred, otp low and all tx outputs will be hiz. t hys otp output reset hysteresis - 7.0 -
4 hv758 electrical characteristics (operating conditions, unless otherwise speci? ed, v ss = 0v, v ll = +3.3v, v dd = +10v, v pp -v pf = +10v, v nn -v nf = -10v, v pp =+90v, v nn = -90v, t a = 25c) output p-channel mosfet, txp (mode 4) symbol parameter min typ max units conditions i out output saturation current 2.2 2.5 - a --- r on channel resistance - 11 - i sd = 100ma c oss output capacitance - 215 - pf v ds = 25v, f = 1.0mhz output n-channel mosfet, txn (mode 4) symbol parameter min typ max units conditions i out output saturation current 2.1 2.2 - a --- r on channel resistance - 11 - i sd = 100ma c oss output capacitance - 90 - pf v ds = 25v, f = 1.0mhz mosfet drain bleed resistor symbol parameter min typ max units conditions r p/n1~4 output bleed resistance 10 15 20 k --- p ro bleed resistors power limit - - 40 mw --- logic inputs symbol parameter min typ max units conditions v ih input logic high voltage (v ll -0.4) - v ll v --- v il input logic low voltage 0 - 0.4 v --- i ih input logic high current - - 10 a --- i il input logic low current -10 - - a --- c in input logic capacitance - - 5.0 pf --- ac electrical characteristics (operating conditions, unless otherwise speci? ed, v ss = 0v, v ll = +3.3v, v dd = +10v, v pp -v pf = +10v, v nn -v nf = -10v, v pp =+90v, v nn = -90v, t a = 25c) symbol parameter min typ max units conditions t r output rise time - 32 - ns 330pf//2.5k load t f output fall time - 32 - ns f out output frequency range 20 - - mhz 100 resistor load hd2 second harmonic distortion - 30 - db t en enable time - 70 250 s t dr delay time on inputs rise - 18 - ns t df delay time on inputs fall - 18 - ns t dm delay on mode change - 2.5 20 s t delay it dr -t df i delay time matching - - 3.0 ns p to n, channel to channel t j delay jitter on rise or fall - 15 - ps v pp /v nn = +/-25v, input t r 50% to hv out t r or t f 50%, with 330pf//2.5k load
5 hv758 switching time diagram truth table (all modes) logic inputs output en pin x nin x txp x txn x 100offoff 1 1 0 on off 101offon 111on*on* 0 x x off off *note: not allowed, may damage ic t dr 50% 10% 50% 90% pinx ninx t df output v nn v pp t r 10% t f 90% 0 drive mode control table mode mc1 mc0 i sc (a) r onp () r onr () 1 0 0 0.58 28 27 2 0 1 0.8 20 19.7 3 1 0 1.35 12 11.7 4 1 1 2.5 6.5 6.3 notes: 1.v pp /v nn = +/-90v, v dd = (v pp - v pf ) = (v nf - v nn ) = +10v 2. i sc is current into 1.0 to gnd 3. r on calculated from v out into 100 load
6 hv758 name function v dd positive internal voltage supply (+10v). v ss power supply return (0v). v ll logic hi voltage reference input (+3.3v). g ref logic low reference, logic ground (0v). v sub substrate of the ic, all v sub pins must connect externally to the most positive potential of the ic. rgnd bleed resistors common return ground. v pp positive high voltage power supply (+90v). v nn negative high voltage power supply (-90v). v pf p-fet drive ? oating power supply, (v pp - v pf ) = +1 0v. v nf n-fet drive ? oating power supply, (v nf - v nn ) = +1 0v. txp1 output p-fet drain (open drain output) for channel 1. txn1 output n-fet drain (open drain output) for channel 1. txp2 output p-fet drain (open drain output) for channel 2. txn2 output n-fet drain (open drain output) for channel 2. txp3 output p-fet drain (open drain output) for channel 3. txn3 output n-fet drain (open drain output) for channel 3. txp4 output p-fet drain (open drain output) for channel 4. txn4 output n-fet drain (open drain output) for channel 4. pin1 input logic control of high voltage output p-fet of channel 1, hi=on, low=off. nin1 input logic control of high voltage output n-fet of channel 1, hi=on, low=off. pin2 input logic control of high voltage output p-fet of channel 2, hi=on, low=off. nin2 input logic control of high voltage output n-fet of channel 2, hi=on, low=off. pin3 input logic control of high voltage output p-fet of channel 3, hi=on, low=off. nin3 input logic control of high voltage output n-fet of channel 3, hi=on, low=off. pin4 input logic control of high voltage output p-fet of channel 4, hi=on, low=off. nin4 input logic control of high voltage output n-fet of channel 4, hi=on, low=off. en chip power enable hi=on, low=off. mc0, mc1 output current mode control pins, see drive mode control table. otp over temperature protection output, open n-fet drain, active low if ic temperature >110c. ball description a1 corner12345678 av pf v pp v pp v nn v nn v nf txn4 txn4 bv pf v pp v pp v nn v nn v nf txp4 txp4 cv dd v sub pin4 nin4 mc0 v sub txn3 txn3 dv ss otp pin3 nin3 mc1 rgnd txp3 txp3 ev ss v ll pin2 nin2 en rgnd txn2 txn2 fv dd v sub pin1 nin1 g ref v sub txp2 txp2 gv pf v pp v pp v nn v nn v nf txn1 txn1 hv pf v pp v pp v nn v nn v nf txp1 txp1 ball con? guration
7 hv758 (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv758 nr061807 64-ball fcbga package outline (fb) 8x8mm body, 2.45mm height (max.), 0.80mm pitch a b c d e f g h 8 7 6 5 4 3 2 1 note 1 (index area d/4 x e/4) seating plane a2 e d e d1 e1 e se sd a detail a a1 top view side view bottom view detail a b symbol a a1 a2 bdd1 e e1 e sdse dimension (mm) min 1.67 0.25 1.32 0.45 7.85 5.60 bsc 7.85 5.60 bsc 0.80 bsc 0.40 bsc 0.40 bsc nom 1.82 0.40 1.42 0.50 8.00 8.00 max 2.45 0.45 2.20 0.55 8.15 8.15 drawings are not to scale. note 1: ball a1 identi? er must be located in the index area indicated. ball a1 corner identi? cation can be used by ink or by metalize d markings, or other features on package body. shape of identi? er is optional.
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